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26 Oct 2021

The open source hardware designed in Barcelona already has the second generation of RISC-V Lagarto processors

The Institute of Microelectronics of Barcelona of the CSIC participates in the creation of this new chip, which has been baptized with the name DVINO. It incorporates a restructuring of the initial design with greater concurrency, as well as some own IP blocks. It is the second generation of open source chips, the first designed in Spain, a project with the Instituto Politécnico Nacional de México, the Barcelona Supercomputing Center, the CSIC, the University of Barcelona and the Universitat Politècnica de Catalunya.

Microprocesador Lagarto RISC-V. Imagen: DRAC project.


The new generation of Lagarto processors, an open source chip based on the ISA RISC-V instruction set, has been shipped to the factory through the European Europractice program. The design, baptized DVINO (acronym for DRAC Vector IN-Order), incorporates many new features to the hardware and is an improvement of the processor that was launched two years ago. The original RISC-V Lagarto processor comes from the IPN in Mexico and is the basis for these initial developments led by the BSC. It is the first processor chip of these characteristics designed in Spain.

The Institute of Microelectronics of Barcelona (IMB-CNM-CSIC) has participated in the creation of this second generation of Lagarto processors together with the Barcelona Supercomputing Center (BSC), which leads the project, the Polytechnic University of Catalonia (UPC), the Instituto Politécnico Nacional of Mexico, and the University of Barcelona, ​​among others. The new design is one of the results of the DRAC project (Designing RISC-V-based Accelerators for next generation Computers), which seeks to facilitate the development of open source hardware in Europe, which has historically depended on US and Asian markets to supply these technological needs.

Mitigate European dependency on processors

The DRAC project has funding from the European Union, which has among its strategic objectives to mitigate European dependence and technological vulnerability in the field of processors. An example of this vulnerability is the recent crisis in the sector, with a shortage of chips in the main technological manufacturing nodes located mainly in the United States and Asia, and the consequent difficulties in the supply of processors.

The final objective of the project is to move towards open source strategies and to be able to offer the processors and the HDL code of its designs openly for use in training, research and development activities. This goal of achieving open hardware and software, indicates Lluís Terés, CSIC researcher at the IMB-CNM, "should lead us to a healthier, open, collaborative competitiveness and, therefore, to better and greater competencies of our ecosystem based on Training-Research-Innovation". A scenario where "the company must play an important role and interact with other actors not only in terms of technology transfer, but also, and more importantly, in terms of close and open collaboration".

"The new design integrates a core of the initial Lagarto with a vector RISC-V processor unit (VPU, Vector Processor Unit) and incorporates some own IP blocks such as a PLL and an ADC-16bits", explains Lluís Terés, who is involved in the project since its inception in 2019.

DVINO has been entirely designed in Barcelona and its main novelties are the update of the ISA to version 2.1, the development of a vector processing unit, the creation of specific IP blocks, to improve clock frequencies (PLL) and facilitate a analog-digital interface with sensors (ADC), as well as the incorporation of new memory controllers (SDRAM or HyperRAM). All this has meant an area increase of x3.5 over the previous prototype in the same technological node, 65nm CMOS.

"The DVINO processor is a very important step in the BSC's strategy to create open source processors developed in Europe and suitable for high-performance computing, the Internet of Things and other domains," explains Miquel Moretó, from the BSC and coordinator of the DRAC project. These plans go ahead with multiple projects led by the BSC such as the exascale experimental platform associated with MareNostrum 5 (MEEP), the European Laboratory of Open Computing Architectures (LOCA), the eProcessor project and the European Processor Initiative (EPI), among others. .

The DRAC project (001-P-001723 ) has been 50% co-financed with € 2.000.000,00by the European Fund for Regional Development of the European Union within the framework of the 2014-2020 ERDF Operational Program of Catalonia, with the support of the Generalitat of Catalonia.