Design flow of the DRAC project
The logic and physical synthesis behind the DRAC project is explained now through a design flow, including the steps of the processors based on the RISC-V architecture.
DRAC is a research project with the aim to produce RISC-V processors and different accelerators trying to achieve the maximum possible performance while minimizing power consumption. To accomplish that, a correct selection of the technological process where the processors will be fabricated is mandatory, as it affects performance, power consumption and fabrication costs. In the DRAC project several technologies have been studied, but the selected one is the 22 nm FDSOI (22FDX) technological process from Globalfoundries (GF), as it allows us to target clock frequencies above 1GHz, it gives us different options to reduce power consumption and the fabrication costs are relatively low.
The DRAC project is a joint collaboration between the Institute of Microelectronics of Barcelona, the Barcelona Supercomputing Center, the Instituto Politécnico Nacional (Mexico) and UPC, among other institutions.
Original source: Barcelona Supercomputing Center.
In the DRAC project we are designing SoCs (System-on-Chip) that include processors based on the RISC-V architecture, different accelerators and a set of analog blocks such as a PLL (Phase-Locked Loop), a SerDes (Serializer Deserializer), an ADC (Analog to Digital Converter) and SPADs (Single Photon Avalanche Diode). Of these analog blocks, the PLL and the SerDes allow to increase the number of instructions executed by the processor; the PLL allows to increase the working frequency while the SerDes enables faster communications with the external memories. Moreover, the ADC allows interaction with analog sensors and SPADs are a tool to enable quantum cryptography.
When planning the integration strategy of the different elements of the SoC, it should be considered that we will work with a mixed signal design. However, as the bigger and the most complex circuits are the digital ones, the chosen strategy is the DoT (Digital On Top). This means that we will start to work as if the SoC were purely digital, and halfway we will add the information of the analog blocks that have been designed separately.
Each analog block is designed following the analog flow, using Cadence®'s "virtuoso" tool. On the other hand, digital designs such as the processor or the accelerators are encoded with RTL (Register-Transfer Level) language, which allows us to describe the behavior of the circuit that we want to design and verify it with simulations. Once we are sure that the designed circuit has the expected behavior, the described behavior needs to be translated into a set of logic gates that perform the same function. This step is called logical synthesis; to carry it out, it is necessary to describe our circuit, to add the information about the available gates of the chosen technology, and to include the constrains of the circuit.
Once the synthesis is finished, we obtain a file, called "netlist", where we will find the digital circuit that we have designed expressed using logic gates available in the chosen technology. The next step consists in distributing the logic cells, analog blocks, GPIOs and memories in a certain area and, in addition, making the connections between them. This step is called physical synthesis, and it can be summarized, very briefly, in 5 stages: Floorplan, Placement, Clock tree synthesis (CTS), Routing and Signoff or Final Verification.
In the Floorplan stage we make the distribution of our SoC, the area that the digital circuits will use, where we are going to place the memories, GPIOs and the analog blocks and how we are going to power the circuits. In the Placement stage, a first arrangement of the logic gates is made to verify that the design can really be implemented, considering the available area and the time constraints that we want to achieve. In the CTS stage, the clock network distribution of the system is implemented. In the Routing stage, the physical connection of the logic gates is made through metal lines. Finally, the Signoff stage serves to close the chip; timing and design rules checks are carried out to find out if the chip meets the timing constraints that we want and if the chip can be manufactured. This stage ends by generating a GDS II file which, in short, is what the semiconductor factory needs to manufacture the chip.
Co-financed by the European Regional Development Fund of the European Union
The DRAC project with file number 001-P-001.723 has been 50% co-financed with € 2,000,000.00 by the European Regional Development Fund of the European Union within the framework of the ERDF Operational Program of Catalonia 2014-2020, with the support of the Generalitat de Catalunya.