#IMBCNMTalks Integration of vertical Single Electron Transistor into CMOS technology
By Alberto del Moral, PhD student at the Nanofabricacion and Nanomechanical Systems Group (NANONEMS), IMB-CNM.
Abstract:
Two of the main drives in semiconductor industry are device miniaturization and power consumption reduction. In the most advanced nodes, three-dimensional architectures have gained significant importance to increase the integration density, being vertically arranged devices the most suitable candidates for the ultimate generations. On the other hand, the increasing number of components arising from the development of the Internet of Things forces to explore new configurations for low power consumption devices, such as Single Electron Transistors (SET).
In this work, the fabrication of a SET based on a vertical nanowire and its co-integration with CMOS technology is addressed, as part of the IONS4SET project. The starting point is a Si/SiO2/Si nanopillar with Si nanodots in the intermediate SiO2 layer, acting as quantum dot between source (bottom part of the pillar) and drain (upper part). The integration process and its optimization are presented. This work also reports the CMOS compatible fabrication of a conventional planar transistor co-integrated with a vertical SET.