This website uses its own and third-party cookies for its operation, to maintain the session and to personalize the user's experience. For more information about the cookies used consult our cookies policy

Institute of Microelectronics of Barcelona IMB-CNM   

IMB-CNM Facebookchannel IMB-CNM Linkedin channel IMB-CNM Youtube channel IMB-CNM Instagram channel IMB-CNM Pinterest channel IMB-CNM RSS channel Contact with IMB-CNM Login to IMB-CNM Intranet

Technology

(1) Layerstack

 

  • 4 inches silicon wafer 500 microns thick
  • 2,5 microns thermal oxide substrate
  • 300 nm Silicon Nitride film
  • 2,0 microns top cladding

Imagen3

 

(2) Processing steps

 

1) Thermal oxide substrate → Oxidize 2,5 microns of the wafer (both sides)
2) LPCVD stoichometric silicon nitride deposition → 300 nm (both sides)
3) Shallow waveguide definition → lithography + 150 nm etching step
4) Deep waveguide definition → lithography + 300 nm etching step
5) Cladding deposition → 2,0 microns PECVD oxide
6) Selective area trench → lithography + 2,0 microns etching on top of the cladding
7) Metalization → lithography + Cr/Au stack patterned to include heaters

(3) Fabricated components

 Imagen4Imagen5Imagen6

Full Review William Hill www.wbetting.co.uk