Institute of Microelectronics of Barcelona IMB-CNM   

IMB-CNM Facebookchannel IMB-CNM Linkedin channel IMB-CNM Youtube channel IMB-CNM Instagram channel IMB-CNM Pinterest channel IMB-CNM RSS channel Contact with IMB-CNM Login to IMB-CNM Intranet
Techniques and processes
  • Thermal oxidation, annealing and diffusion processes
  • Thin film deposition by Chemical Vapor Deposition (LPCVD and PECVD)
  • Deposition of high-k dielectrics by Atomic Layer Deposition (ALD)
A – OXIDE GROWTH

Technique:

The silicon oxide growth is performed on silicon wafers with their surface full or partially exposed to the oxidation ambient of the chamber. The oxidation process is carried out in specifically designed furnaces inside of which temperature, purity of reaction gases and whole environment cleanliness are strictly controlled. Depending on the required oxide quality and its thickness, the growth is performed under oxygen ambient (dry oxidation), in water steam ambient (wet oxidation) or with the addition of chloride compounds to passivate metallic impurities. The process temperature is conveniently selected depending on the required quality and thickness of the oxide layer, but also it is conditioned by the substrate nature and the maximum thermal load that is allowed in each particular technology.

Available capabilities:

  • Silicon oxide growing. Thickness range from 5nm up to 2000nm
  • In-wafer and wafer to wafer uniformity below 1%
  • O2, H2O and chlorine ambient
  • Rapid thermal oxidation (RTO) available
  • Silicon substrates of 100mm diameter or below
  • Possibility of processing samples of other materials (SiC, sapphire, quartz...) and sizes up to 150mm

Equipment units:

  • LB 45 ASM - 2 racks of 4 horizontal diffusion furnaces with automatic boat loaders. CMOS (clean) line.
  • DWEL 9/20 BTS Engineering – 2 horizontal diffusion furnaces with automatic boat loaders for wafers up to 150mm. CMOS (clean) line or metal contaminated samples are allowed.
  • Annealsys ASMaster-2000 RTCVD furnace, for CMOS (clean) line substrates up to 150mm.
 
B – DIFFUSION AND ANNEALING

Technique:

Diffusion is the process by which a species moves in a given environment due to a spatial gradient in concentration. Diffusion processes in the field of microelectronics, are those that allow the spatial and in-depth definition of the substrate regions with different dopant species (mainly, boron and phosphorus) that are in the base the semiconductor industry. An annealing is a thermal process in which the substrates are exposed to different temperatures, times and environments depending on the pursued objective.

The most common purposes of those thermal treatments are the predeposition of doping species and their spatial redistribution, the post-implant annealing for impurities activation, the fluidization of interlevel dielectric layers, annealing of aluminum layers for contacts formation and the densification of different deposited layers.

Available capabilities:

  • Annealing temperature range: from 600ºC to 1200ºC
  • Diffusion ambient: N2, O2, Ar, N2-H2, H2O
  • Phosphorus predeposition from POCl3 (liquid source)
  • Boron predeposition from BN/B2O3 (solid source)
  • Al annealing and annealing in N2-H2 ambient: between 250ºC and 450ºC
  • For silicon wafers of 100mm diameter or below
  • Possibility of processing other substrate materials (SiC, sapphire...) and wafer sizes up to 150mm diameter
  • Thermal annealing of polyimide and other substrates with contaminant metals (designed as non-suited for clean CMOS line because of the presence of contaminant metals or traces of them)

Equipment units: (the same ones as in the oxidation module)

C- THIN FILM DEPOSITION BY LPCVD AND PECVD

Technique (LPCVD):

The vapor phase chemical deposition at low pressure (LPCVD) consists in the process of deposition of a stable layer onto a blanket or partially processed substrate, by means of a controlled chemical reaction of some gaseous species, named the precursors. The distinctive features of this kind of process are the fact that all the elements that form the deposited layers come from the outside of the reactor, that the reaction takes place at low pressures (commonly between 0.1 and 1 Torr) and at high temperatures (between 500ºC and 900ºC), factors that lead to obtain a good uniformity and step coverage.

Available capabilities:

  • Silicon nitride deposition (Si3N4) at 800ºC, for thicknesses between 10nm and 500nm
  • Polysilicon deposition (not doped in-situ) at 630ºC, for thicknesses between 30nm and 5μm
  • Amorphous silicon (α-Si) at 580ºC, for thicknesses from 30nm to 1μm
  • Wafer uniformity better than 3-5%
  • Horizontal LPCVD furnaces for batch processing of wafers and substrate both sides layer deposition at a time
  • Best suited for silicon wafers of 100mm or below. Only CMOS clean line substrates are allowed, no metal contaminated substrates are accepted.

Equipment units:

  • ETNA HT-210 Semi Engineering, T10 – LPCVD tubular furnace for Si3N4 deposition
  • ETNA HT-210 Semi Engineering, T11 - LPCVD tubular furnace for Polisilicio/α-Si deposition
 

Technique (PECVD):

The Plasma Enhanced Chemical Vapor Deposition consists also in a process for deposition of a stable layer on top of a blanket or partially processed substrate, by means of the chemical reaction of gaseous species. This process constitutes a particular case of LPCVD that takes place at under atmospheric pressures (commonly between 1 and 10 Torr), and that is characterized by its low reaction temperatures (usually lower than 400ºC), achieved thanks to the extra energy intake given by the plasma generation.

The most common uses of this technique are the deposition of dielectric layers for the passivation of samples, the deposition of interlevel or intermetallic dielectric layers, structural layers in MEMS and opto-electromechanical structures.

Available capabilities:

  • Silicon nitride deposition at 300ºC-400ºC, for thicknesses between 50nm and 1μm
  • Silicon oxide deposition at 300ºC-400ºC, for thicknesses from 50nm to 5μm
  • Deposition of silicon oxide doped with B or P for the formation of BPSG (borophosphosilicate glass) layers useful as dielectric interlevel layers with smoothing topography capabilities
  • Deposition of oxinitrides, and non-stoichiometric silicon oxide and nitride layers and silicon oxide layers with several refractive index
  • Amorphous silicon deposition (a-Si:H)
  • Wafer uniformity lower than 5-10%, depending on the kind of deposited layer and the specified thickness
  • Deposition in only one side of the sample at a time

Equipment units:

  • ETNA HT-210 Semi Engineering, T12 – tubular furnace with special graphite boat and plasma generator of 40kHz, for SiNx, SiOx deposition
  • OXFORD PLASMALAB 800 Plus – horizontal multiwafer chamber (up to 8 100mm diameter wafers). Manual loading. Two plasma generators: an RF one at 13.56MHz and an LF one (50-400kHz). Working temperatures lower than 400ºC and pressure range between 100mT and 2T. Suitable for metal contaminated samples (not for CMOS line clean samples)
  • AMAT Precision 5000 Mark II, automatic PECVD system with 3 chambers for the deposition of SiNx, SiOx layers from silane or from TEOS. BPSG layer deposition at 430ºC.
 
D- ALD DIELECTRICS DEPOSITION

Technique:

The Atomic Layer Deposition (ALD) is a particular case of CVD that consists in the deposition of a stable layer on top of a bare or partially processed substrate by means of the sequential production of gas-solid self-limiting reactions, achieved through the alternated precursor expositions.

ALD is therefore a very good suited technique for the synthesis of thin solid layers of inorganic materials even as thin as one molecular monolayer. These layers exhibit two distinctive features: a great uniformity at atomic level in their physical properties (thickness, density, composition, etc.) and perfect conformality.

Available capabilities:

  • Al2O3 deposition between 100ºC and 300ºC, for layer thickness from 1nm to 50nm
  • HfO2 deposition between 150ºC and 350ºC, for layer thickness from 1nm to 50nm
  • TiO2 deposition between 150ºC and 300ºC, for layer thickness from 1nm to 50nm
  • Nanolaminates of aluminum oxide, hafnium oxide and titanium oxide
  • Availability of 2 oxidant precursors: H2Od.i. and O3
  • In-wafer thickness uniformity around 1-2%
  • Substrate one side deposition at a time

Equipment units:

  • Cambridge Nanotech Savannah 200
 

 

Contact person

This email address is being protected from spambots. You need JavaScript enabled to view it.

Full Review William Hill www.wbetting.co.uk